VLSI System Design

Course | Master of Science in Electrical Engineering
Semester: Spring 2025
Instructor: Dr. Steve Undy

Course Overview

This course provides a comprehensive introduction to VLSI chip design. Combining theory with hands-on labs, it covers everything from MOS transistor fundamentals to chip layout, fabrication, and verification. We gained practical experience using Cadence design tools to complete the full design cycle—logic design, circuit simulation, layout, and testing. The course emphasizes optimizing delay, power, and timing while addressing interconnect challenges and robust chip verification techniques.

Technical Scope

• Full VLSI Design Cycle:
  Experience in all design stages, including logic and circuit design, layout creation, fabrication understanding, and design verification.

• Design Tools:
  Proficient use of Cadence Virtuoso and related Cadence suites for schematic capture, SPICE simulation, layout design, and design verification.

• Device Physics & CMOS Technology:
  Deep understanding of MOS transistor behavior, CMOS fabrication processes, and layout design rules critical to accurate modeling and implementation.

• Circuit Design & Optimization:
  Design and simulation of combinational and sequential logic circuits with emphasis on optimizing delay, power consumption, and interconnect performance.

• Timing & Clocking:
  Applied knowledge of timing analysis, metastability challenges, clock distribution, and clock system design for robust synchronous operation.

• Verification, Testing & Debugging:
  Use of industry techniques for design verification, debugging, fault detection, and implementation of design-for-test (DFT) methodologies.

• Performance Analysis:
  Focused on delay modeling, power optimization, interconnect effects, and ensuring chip robustness through comprehensive testing and validation.

Project: 8-bit Asynchronous Multiplier

In this project, I designed an 8-bit asynchronous multiplier with an active-low global clear signal and a 16-bit output to prevent overflow. The design met a minimum input data rate of 1 MHz with 1 pF output load capacitance, while ensuring that inputs are ignored during reset. I focused on selecting appropriate standard cells, optimizing gate sizing, and verifying functionality through testbenches—balancing power efficiency, timing accuracy, and design reliability.

Final Reflection

This course gave me a strong foundation in VLSI chip design while also building practical problem-solving and collaboration skills. Working through the full design cycle sharpened my ability to approach complex challenges, verify designs, and optimize for performance, power, and reliability. These experiences prepared me to contribute effectively to industry teams in semiconductor design, embedded systems, and hardware engineering.